This invention relates to a potential data selection circuit adapted for selecting any one of a plurality of potential data to output the selected data to the external.
In recent years, such potential data selection circuits have been used as devices for driving liquid crystal panels.
The circuit configuration of a conventional potential data selection circuit is shown in FIG. 1. This potential data selection circuit includes a sample-hold circuit 11, a decoder 13, and a multiplexer 175. The sample-hold circuit 11 is adapted so that data DaO and DbO for selecting potential data are inputted thereto to hold them, and includes clocked inverters 11a1 and 11b1 operative in response to an inputted clock .phi.L, clocked inverters 11a3 and 11b3 operative in response to an inputted clock bar .phi.L, and inverters 11a2 and 11b2. The input terminal of the clocked inverter 11a1 is connected to the input terminal to which data DaO is inputted. The input terminal of the inverter 11a2 is connected to the output terminal of the clocked inverter 11a1. A node N1a is connected to the output terminal of the inverter 11a2. The input terminal of the clocked inverter 11a3 is connected to the output terminal of the inverter 11a2. The output terminal of the clocked inverter 11 a3 is connected to the input terminal of the inverter 11a2. Similarly, on the input terminal side where data DbO is inputted, the input terminal of the clocked inverter 11b1 is connected thereto, and the input terminal of the inverter 11b2 is connected to its output terminal. A node N1b is connected to the output terminal of the inverter 11b2. In addition, the input terminal of the clocked inverter 11b3 is connected to the output terminal of the inverter 11b2, and the output terminal of the clocked inverter 11b2 is connected to the input terminal of the inverter 11b2.
The decoder 13 is adapted so that data held in the sample-hole circuit 11 are given thereto to decode those data, and includes inverters 13a2, 13b2, 13c2, 13d2, 13f, 13g, and NOR gates 13a1, 13b1, 13c1, 13d1. To the node N1a on the output side of the sample-hold circuit 11, the input terminal of the inverter 13g and the input terminals of the NOR gates 13a1 and 13b1 are connected. Further, to the node N1b, the input terminal of the inverter 13f and the input terminals of the NOR gates 13a1 and 13c1 are connected. The output terminal of the inverter 13g is connected to the input terminals of the NOR gates 13c1 and 13d1, and the output terminal of the inverter 13f is connected to the input terminals of the NOR gates 13b1 and 13d1. The output terminal of the NOR gate 13a1 is connected to a node N2a2, and is connected to a node N2a1 through the inverter 13a2. The output terminal of the NOR gate 13b1 is connected to a node N2b2, and is connected also in parallel with a node N2b1 through the inverter 13b2. The output terminal of the NOR gate 13c1 is connected to a node N2c2, and is further connected to a node N2c1 through the inverter 13c2. In addition, the output terminal of the NOR gate 13d1 is connected to a node N2d2, and is also connected to a node N2d1 through the inverter 13d2.
The multiplexer 175 is adapted so that signals decoded by the decoder 13 and outputted therefrom are given thereto to select any one of signals to output the selected signal. This multiplexer 175 comprises an analog switch 175a including a P-channel transistor 175a1 and an N-channel transistor 175a2, an analog switch 175b including a P-channel transistor 175b1 and an N-channel transistor 175b2, an analog switch 175c including a P-channel transistor 175c1 and an N-channel transistor 175c2, and an analog switch 175d including a P-channel transistor 175d1 and an N-channel transistor 175d2.
In the analog switch 175a, the P-channel transistor 175a1 and the N-channel transistor 175a2 are connected in parallel, nodes N2a1 and N2a2 are respectively connected to their gates, and potential data Va is inputted to one end of the analog switch 175a. In the circuit 175b, the P-channel transistor 175b1 and the N-channel transistor 175b2 are connected in parallel, nodes N2b1 and N2b2 are respectively connected to their gates, and potential data Vb is inputted commonly to one end of the circuit 175b. In the analog switch 175c, the P-channel transistor 175c1 and the N-channel transistor 175c2 are connected in parallel, nodes N2c1 and N2c2 are respectively connected to their gates, and potential data Vc is inputted commonly to one end of the analog switch 175c. In the analog switch 175d, the P-channel transistor 175d1 and the N-channel transistor 175d2 are connected in parallel, nodes N2d1 and N2d2 are respectively connected to their gates, and potential data Vd is inputted commonly to one end of the analog switch 175d.
The operation of the potential data selection circuit thus constituted will now be described with reference to timings of FIG. 2. Data DaO, DbO are inputted to the sample-hold circuit 11. Further, a clock .phi.L and a clock bar .phi.L are inputted to the clocked inverters 11a1, 11a3, 11b1 and 11b3. In synchronism with the timing at which the clock .phi.L rises, data DaO, DbO are respectively sampled and held. These data are outputted as the held data Da1, Db1 from the nodes N1a and N1b of the sample-hold circuit 11.
These data Da1, Db1 are inputted to the decoder 13, at which they are decoded. Thus, a control signal 13a, a control signal bar 13a, a control signal 13b, a control signal bar 13b, a control signal 13c, a control signal bar 13c, a control signal 13d, and a control signal bar 13d are outputted from nodes N2a2, N2a1, N2b2, N2b1, N2c2, N2c1, N2d1 and N2d2, respectively. For example, in the case where data Da1, Db1 are all at logic "1" level, the control signal 13d is caused to be at logic "1" level, and the control signal bar 13d is caused to be at logic "0" level. Other control signals 13a, 13b and 13c are caused to be at logic "0" level, and control signal bar 13a, the signal bar 13b and the signal bar 13c are caused to be at logic "1" level.
These signals are inputted to the multiplexer 175. Only in the circuit 175d of these circuits 175a-175d, the P-channel transistor 175d1 and the N-channel transistor 175d2 are both turned ON. In other circuits 175a-175c, all transistors are turned OFF. Thus, only potential data Vd delivered to the circuit 175d of potential data Va, Vb, Vc and Vd is outputted to the exterior as an output Q.
In a manner as stated above, any one of analog switches 175a-175d is turned ON by combination of logic levels of selection data DaO, DbO input to the sample-hold circuit 11. As a result, any one of potential data Va-Vd is selected and the selected data is outputted.
The conventional circuit described above, however, has the following problems. In the case where a large capacity load is connected to the output terminal of the multiplexer 175, the drive speed is unable to be high unless the sizes of the analog switches 175a-175d are caused to be large to increase the respective output currents. Further, in order to increase such output currents, the widths of wires for delivering data potentials Va-Vd to the analog switches 175a-175d must be broadened in order that any electro-migration does not take place in wiring layers comprised of aluminum, etc.
In the liquid crystal panel, there is a tendency for the number of potential data to be selected and outputted to increase. Therefore, it is a problem that if the number of potential data increases, the area of the mask pattern would increase.